1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, especially to a current generator preventing its output ringing.
2. Background of the Invention
A converter for converting a signal from digital to analog (hereinafter referred to as xe2x80x9cD/A convertersxe2x80x9d), especially a current output type D/A converter, is an aggregate of current generators each including 2Nxe2x88x921 constant current sources for N input digital bits and outputting current corresponding to the number of input digital bits. In the following, the structure of a typical D/A converter and problems thereof will be described.
First, we will describe the structure of a typical D/A converter 90 with reference to FIG. 30. The D/A converter 90 is mainly composed of a plurality of current source cells CL, and moreover includes a decoder/clock buffer portion DB connected to the current source cells CL, a bias circuit BC, and so on. Each of the current source cells CL has two output nodes I1 and I2 connected to output terminals IT and {overscore (IT)}, respectively. The output terminal IT is grounded via an external resistance R2, and the output terminal {overscore (IT)} is directly grounded.
Next, we will describe the structure of the current source cell CL that is composed of a current generator CG and a driver circuit DC.
The current generator CG is composed of P-channel MOSFETs, including a constant-current-source transistor M1 connected at its source electrode to a power supply VDD, for generating constant current in response to a bias signal BS applied from the bias circuit BC, and transistors M2 and M3 each connected at its source electrode to a drain electrode of the transistor M1. The drain electrodes of the transistors M2 and M3 correspond to the output nodes I1 and I2, respectively. On receipt of control signals from the driver circuit DC, the transistors M2 and M3 complementarily operate to function as current switches (first and second switch means).
The driver circuit DC is composed of inverter circuits IV2 and IV3 connected at their outputs to the transistors M2 and M3, respectively. The inverter circuit IV2 comprises a P-channel transistor M6 and an N-channel transistor M7 connected in series between the power supply VDD and the ground, and each receiving a selection signal SL at its gate electrode. The inverter circuit IV3 comprises a P-channel transistor M8 and an N-channel transistor M9 connected in series between the power supply VDD and the ground, and each receiving a selection signal {overscore (SL)} at its gate electrode. The selection signals SL and {overscore (SL)} are applied from a decoder of the decoder/clock buffer portion DB.
The current-output type D/A converter 90 with such a structure has faced a problem that recent high speed in D/A conversion increases variations in output current per unit of time, thereby causing ringing in the output waveform.
FIG. 31 shows such an output waveform with ringing. The horizontal axis indicates time, and the vertical axis indicates an output voltage. As shown, ringing mostly occurs on the top portion that is originally supposed to be flat and near the falling edge of the output waveform. As a fluctuation in the output waveform, the ringing must be reduced at any cost to secure the quality of the analog output.
Referring to FIG. 32, we will now describe the cause of the ringing. FIG. 32 shows inductance components and capacitive components, which are parasitic on the D/A converter 90 in FIG. 30, as inductance and capacitance, respectively.
As shown in FIG. 32, there are parasitic inductance L1 between the power supply VDD and the source electrode of the transistor M1 (connected to a power terminal PT), parasitic capacitance C3 between the source electrode of the transistor M1 and the drain electrode of the transistor M2, parasitic capacitance C4 between the source electrode of the transistor M1 and the drain electrode of the transistor M3, parasitic capacitance C5 between the drain electrode of the transistor M2 and a substrate SS, and parasitic capacitance C6 between the drain electrode of the transistor M3 and the substrate SS.
Further, there are parasitic inductance L2 between the output terminal IT and the external resistance R2, parasitic inductance L3 between the output terminal {overscore (IT)} and the ground GND, and parasitic capacitance C2 in parallel with the external terminal R2.
The ringing is caused by a resonance of the parasitic inductance and the parasitic capacitance. Especially, it is considerably enlarged in the presence of the circuit that includes only the parasitic inductance and the parasitic capacitance on its path from the power supply VDD to the ground GND, or in the presence of a loop circuit that is composed only of the parasitic inductance and the parasitic capacitance.
As an example of the circuit that includes only the parasitic inductance and the parasitic capacitance on its path from the power supply VDD to the ground GND, a first LC circuit PS1 is shown in bold type in FIG. 33. This circuit is composed of the power supply VDD, the parasitic inductance L1, the parasitic capacitance C4, the parasitic inductance L3, and the ground GND. FIG. 33, given for explanation of this circuit, is basically the same as FIG. 32.
As another example of such a circuit, a second LC circuit PS2 is shown in bold type in FIG. 34. This circuit is composed of the power supply VDD, the parasitic inductance L1, the parasitic capacitance C3, the parasitic inductance L2, the parasitic capacitance C2, and the ground GND. FIG. 34, given for explanation of this circuit, is basically the same as FIG. 32.
As an example of the loop circuit that is composed only of the parasitic inductance and the parasitic capacitance, third and fourth circuits PS3 and PS4 are shown in bold type in FIG. 35. The third circuit PS3 is composed of the substrate SS, the parasitic capacitance C5, the parasitic inductance L2, the parasitic capacitance C2, and the ground GND, and the fourth circuit PS4 is composed of the substrate SS, the parasitic capacitance C6, the parasitic inductance L3, and the ground GND. If a P-type semiconductor substrate is used, these two circuits are looped because the substrate potential becomes the ground potential. FIG. 35, given for explanation of the third and the fourth circuits, is basically the same as FIG. 32.
This ringing problem has not been characteristic of the current generator in the D/A converter, but common to the semiconductor integrated circuit devices with similar structures.
A first aspect of the present invention is directed to a semiconductor integrated circuit device comprising: a constant current source connected to a first power supply via a power terminal; first and second current switches connected to the output of the constant current source in parallel with each other, for outputting the output of the constant current source complementarily as first and second outputs respectively on the basis of first and second control signals complementarily applied from driving means; first and second terminals receiving the first and the second outputs, respectively; a first resistive element provided on at least either one of a first path connecting the first current switch and the first terminal and a second path connecting the second current switch and the second terminal.
Preferably, according to a second aspect of the present invention, the first terminal outputs the first output to the outside as the output of the semiconductor integrated circuit device; the second terminal connects the second output to a second power supply; and the first resistive element is provided on the second path.
Preferably, according to a third aspect of the present invention, the first terminal outputs the first output to the outside as the output of the semiconductor integrated circuit device; the second terminal connects the second output to a second power supply; and the first resistive element includes a first element provided on the first path and a second element provided on the second path.
Preferably, according to a fourth aspect of the present invention, the constant current source, the first current switch, and the second current switch are first to third transistors of a first conductivity type, respectively. The first transistor is connected at its first main electrode to the power terminal and at its second main electrode to respective first main electrodes of the second and the third transistors, and the second transistor and the third transistor are connected at their second main electrodes to the first path and the second path, respectively. The driving means comprises: a first inverter circuit having a fourth transistor of the first conductivity type that is connected at its first main electrode to the first power supply, and a fifth transistor of a second conductivity type that is connected at its first main electrode to the second power supply and at its second main electrode to a second main electrode of the fourth transistor. The first inverter circuit inverts a first signal that is applied at respective control electrodes of the fourth and the fifth transistors, and outputs the inverted first signal as the first control signal from a connected portion between the second main electrodes of the fourth and the fifth transistors, the connected portion being an output portion. The driving means further comprises a second inverter circuit having a sixth transistor of the first conductivity type that is connected at its first main electrode to the first power supply, and a seventh transistor of the second conductivity type that is connected at its first main electrode to the second power supply and at its second main electrode to a second main electrode of the sixth transistor. The second inverter circuit inverts a second signal that is applied at respective control electrodes of the sixth and the seventh transistors, and outputs the inverted second signal as the second control signal from a connected portion between the second main electrodes of the sixth and the seventh transistors, the connected portion being an output portion. The driving means further comprises a second resistive element electrically connected between the output portions of the first and the second inverter circuits.
Preferably, according to a fifth aspect of the present invention, the second resistive element is a resistance.
Preferably, according to a sixth aspect of the present invention, the second resistive element is composed of: an eighth transistor having a first main electrode connected to the first inverter circuit, a second main electrode connected to the second inverter circuit, and a control electrode having a diode connection; and a ninth transistor having a first main electrode connected to the second inverter circuit, a second main electrode connected to the first inverter circuit, and a control electrode having a diode connection.
Preferably, according to a seventh aspect of the present invention, the driving means further comprises: first cutoff means provided between the second main electrode of the eighth transistor and the output portion of the second inverter circuit, the first cutoff means receiving a cutoff signal and cutting off a path that electrically connects the second main electrode of the eighth transistor and the output portion of the second inverter circuit; and second cutoff means provided between the second main electrode of the ninth transistor and the output portion of the first inverter circuit, the second cutoff means receiving the cutoff signal and cutting off a path that electrically connects the second main electrode of the ninth transistor and the output portion of the first inverter circuit.
Preferably, according to an eighth aspect of the present invention, the first cutoff means and the second cutoff means are tenth and eleventh transistors, respectively; and the cutoff signal is applied to respective control electrodes of the tenth and the eleventh transistors.
Preferably, according to a ninth aspect of the present invention, the constant current source, the first current switch, and the second current switch are first to third transistors of a first conductivity type, respectively. The first transistor is connected at its first main electrode to the power terminal and at its second main electrode to respective first main electrodes of the second and the third transistors, and the second transistor and the third transistor are connected at their second electrodes to the first path and the second path, respectively. The driving means includes an inverter circuit having a fourth transistor of the first conductivity type that is connected at its first main electrode to the first power supply, a fifth transistor of a second conductivity type that is connected at its first main electrode to the second power supply and at its second main electrode to a second main electrode of the fourth transistor, and a first resistance provided between the first and the second main electrodes of the fourth transistor. The inverter circuit inverts a signal that is applied at respective control electrodes of the fourth and the fifth transistors, and outputs the inverted signal as the first or second control signal from a connected portion between the second main electrodes of the fourth and the fifth transistors, the connected portion being an output portion.
Preferably, according to a tenth aspect of the present invention, the constant current source, the first current switch, and the second current switch are first to third transistors of a first conductivity type, respectively. The first transistor is connected at its first main electrode to the power terminal and at its second main electrode to respective first main electrodes of the second and the third transistors, and the second transistor and the third transistor are connected at their second main electrodes to the first path and the second path, respectively. The driving means includes an inverter circuit having a fourth transistor of the first conductivity type that is connected at its first main electrode to the first power supply, a fifth transistor of a second conductivity type that is connected at its first main electrode to the second power supply and at its second main electrode to a second main electrode of the fourth transistor, a first resistance provided between the first and the second main electrodes of the fourth transistor, and a second resistance provided between the first and the second main electrodes of the fifth transistor. The inverter circuit inverts a signal that is applied at respective control electrodes of the fourth and the fifth transistors, and outputs the inverted signal as the first or second control signal from a connected portion between the second main electrodes of the fourth and the fifth transistors, the connected portion being an output portion.
Preferably, according to an eleventh aspect of the present invention, the power terminal, a power path connecting the constant current source and the power terminal, the first terminal, the first path, the second terminal, the second path, and the first resistive element are provided on an well region of a second conductivity type that is formed in the surface of a semiconductor substrate of a first conductivity type and is electrically connected to the first power supply.
Preferably, according to a twelfth aspect of the present invention, the well region is electrically connected to the first power supply via a third resistive element.
Preferably, according to a thirteenth aspect of the present invention, the first path and the second path are provided on each side of the power path in parallel with each other.
A fourteenth aspect of the present invention is directed to a semiconductor integrated circuit device formed on a semiconductor substrate of a first conductivity type. The device comprises: a path provided in a region except an element-forming region where an element to specify the operation of the semiconductor integrated circuit device is formed. The path is formed of a conductive layer electrically connected to the element-forming region. Further, the path is provided on a well region of a second conductivity type that is formed in the surface of the semiconductor substrate of the first conductivity type and is electrically connected to an operating power of the semiconductor integrated circuit device.
Preferably, according to a fifteenth aspect of the present invention, the well region is electrically connected to the operating power via a resistive element.
A sixteenth aspect of the present invention is directed to a semiconductor integrated circuit device comprising: a current generator including a transistor for outputting current in response to a bias signal applied at its control signal, and a resistance connected at its one end to the control electrode of the transistor; bias-signal supply means for supplying the bias signal via a bias-signal line connected to the other end of the resistance; and a capacitor provided between the bias-signal line and a predetermined power supply. In the device, a line width of the resistance is set wide enough to be resistant to a surge voltage to be applied from the predetermined power supply side via the capacitor.
In the semiconductor integrated circuit of the first aspect, the first resistive element is provided on at least either one of the first and the second paths, which eliminates at least either one of two paths each composed only of the parasitic inductance and the parasitic capacitance that are parasitic on the current paths from the first power supply through the constant current source and the first or second switch to the first or second terminal. This achieves damping of oscillation due to a resonance of the parasitic inductance and the parasitic capacitance.
In the semiconductor integrated circuit device of the second aspect, the first resistive element is provided on the second path, which eliminates a path composed only of the parasitic inductance and the parasitic capacitance that are parasitic on the current path from the first power supply through the constant current source, the second current switch and the second terminal to the second power supply. This achieves damping of oscillation due to the resonance of the parasitic inductance and the parasitic capacitance on that path.
In the semiconductor integrated circuit device of the third aspect, the first element is provided on the first path, which eliminates a path composed only of the parasitic inductance and the parasitic capacitance that are parasitic on the current path from the first power supply through the constant current source and the first current switch to the first terminal. Further, the second element is provided on the second path, which eliminates a path composed only of the parasitic inductance and the parasitic capacitance that are parasitic on the current path from the first power supply through the constant current source, the second current switch, and the second terminal to the second power supply. Thus, the device achieves damping of oscillation due to the resonance of the parasitic inductance and the parasitic resistance.
In the semiconductor integrated circuit device of the fourth aspect, when the first signal is applied to turn on the fourth transistor, for example, a current path is formed from the first power supply through the fourth transistor, the second resistive element and the seventh transistor to the second power supply, and the second control signal whose reference potential is closer to the potential of the first power supply than the potential of the second power supply, is applied to the third transistor. This resolves the problem that, when first resistive element is provided on the second path, potential difference between the second main electrode of the third transistor and the second control signal is reduced so that the third transistor does not operate in the saturation region. Similarly, operating imperfection of the second transistor, occurring when the first resistive element is provided on the first path, can be eliminated.
In the semiconductor integrated circuit device of the fifth aspect, the second resistive element is readily formable because it is composed of the resistance.
In the semiconductor integrated circuit device of the sixth aspect, it is possible to obtain on-state resistance of the eighth and the ninth transistors having a diode connection, so that the equivalent resistance value is obtained with smaller area than in the device having the second resistive element in the form of resistance. This achieves downsizing of the device.
In the semiconductor integrated circuit device of the seventh aspect, the current flowing through the second resistive element can be cut off optionally by the first and the second cutoff means on the basis of the cutoff signal. This prevents a constant current flow to the second resistive element, thereby reducing wasteful current consumption.
In the semiconductor integrated circuit device of the eighth aspect, the first cutoff means and the second cutoff means are composed of the tenth and the eleventh transistors, respectively. Thus, when the current flow is not cut off, more on-state resistance can be obtained in addition to the on-state resistance of the eighth and the ninth transistors.
In the semiconductor integrated circuit device of the ninth aspect, when the first signal is applied to turn on the fifth transistor, current flows from the first power supply to the first resistance, and the first or second control signal whose reference potential is closer to the potential of the first power supply than that of the second power supply, is applied from the output end of the inverter circuit. This resolves the problem that, when the inverter circuit is connected to the control electrode of the third transistor by the first resistive element provided on the second path, potential difference between the second main electrode of the third transistor and the second control signal is reduced so that the third transistor does not operate in the saturation region. Similarly, operating imperfection of the second transistor, occurring when the inverter circuit is connected to the control electrode of the second transistor by the first resistive element on the first path, can be eliminated.
In the semiconductor integrated circuit device of the tenth aspect, when the first signal is applied to turn on the fifth transistor, current flows from the first power supply to the first resistance, and the first or second control signal whose reference potential is closer to the potential of the first power supply than that of the second power supply, is applied from the output portion of the inverter circuit. On the contrary, when the first signal is applied to turn off the fifth transistor, current flows from the second power supply to the second resistance, and the first or second control signal whose reference potential is closer to the potential of the second power supply than that of the first power supply, is applied from the output portion of the inverter circuit. This reduces variations in the first or second control signal, thereby reducing fluctuations in the outputs of the second and the third transistors.
In the semiconductor integrated circuit device of the eleventh aspect, the power terminal, the power path connecting the constant current source and the power terminal, the first terminal, the first path, the second terminal, the second path, and the first resistive element are provided above the well region of the second conductivity type that is electrically connected to the first power supply. Thus, the parasitic capacitance between those terminals or paths and the well region, and the parasitic capacitance between the well region and the semiconductor substrate are connected in series. This reduces the parasitic capacitance, thereby achieving damping of oscillation due to the resonance of the parasitic inductance and the parasitic capacitance.
In the semiconductor integrated circuit device of the twelfth aspect, the well region that is electrically connected to the first power supply via the third resistive element achieves further damping of oscillation due to the resonance of the parasitic inductance and the parasitic capacitance.
In the semiconductor integrated circuit device of the thirteenth aspect, the first path and the second path are provided on each side of the power path in parallel with each other, so that the flow of current through one terminal is opposite to that through the adjacent terminals. This allows mutual inductance between the adjacent terminals to reduce the influence of self inductance at each terminal.
In the semiconductor integrated circuit device of the fourteenth aspect, the parasitic capacitance between the conductive layer and the well region, and the parasitic capacitance between the well region and the semiconductor substrate are connected in series, because the path formed of the conductive layer is provided above the well region of the second conductivity type that is electrically connected to the operating power of the semiconductor integrated circuit device. This reduces the parasitic capacitance, thereby achieving damping of oscillation due to the resonance of the parasitic inductance and the parasitic capacitance.
In the semiconductor integrated circuit device of the fifteenth aspect, the electrical connection of the well region and the operating power via the resistive element allows further damping of oscillation due to the resonance of the parasitic inductance and the parasitic capacitance.
The semiconductor integrated circuit device of the sixteenth aspect can prevent damage to the current-source transistor by the application of the surge voltage. Further, when including a plurality of current generators, the device can prevent propagation of potential fluctuations at the control electrode of the current-source transistor in one current generator to other current-source transistors in other current generators, as well as crosstalk between the current generators.
Thus, an object of the present invention is to provide the semiconductor integrated circuit device reducing its output ringing and preventing imperfections due to the application of the structure to reduce the ringing.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.